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www.semtech.com page 1 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech description features the SX8724S is a data acquisition system based on semtech's low power zoomingadc? technology. it directly connects most types of miniature sensors with a general purpose microcontroller. with 3 differential inputs, it can adapt to multiple sensor systems. its digital outputs are used to bias or reset the sensing elements. up to 16-bit differential data acquisition programmable gain: (1/12 to 1000) sensor offset compensation up to 15 times full scale of input signal 3 differential or 6 single-ended signal inputs programmable resolution versus speed versus supply current digital outputs to bias sensors internal or external voltage reference internal time base low-power (250 ua for 16b @ 250 s/s) spi interface, 2 mbps serial clock applications ordering information industrial pressure sensing industrial temperature sensing industrial chemical sensing barometer compass device package reel quantity SX8724Swltdt mlpq-w-16 4x4 1000 - available in tape and reel only - weee/rohs compliant, pb-free and halogen free. functional bloc diagram ac0 signal mux + - + - ref mux ready ac3 ac2 ac1 pga adc v ref + - zoomingadc tm vpump vbatt d1/vref,in d0/vref,out SX8724S vss control logic gpio charge pump 4mhz osc ac5 ac4 ac7 ac6 mosi miso/ready spi sclk ss mcu
revision 1.0 february 2011 ? semtech www.semtech.com /products/ page 2 section page table of content advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition e lectrical s pecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 por timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 spi interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.3 spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 c ircuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 bloc diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 vref. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3.1 optional operating mode: external vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5.1 wake-up from sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 zoomingadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.1 acquisition chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.2 programmable gain amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1.3 pga & adc enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 zoomingadc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 input multiplexers (amux and vmux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 first stage programmable gain amplifier (pga1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 second stage programmable gain amplifier (pga2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6 third stage programmable gain amplifier (pga3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.7 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7.1 conversion sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7.2 over-sampling frequency (fs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.3 over-sampling ratio (osr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.4 number of elementary conversions (nelconv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.5 resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.7.6 conversion time & throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.7.7 continuous-time vs. on-request conversi on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.7.8 output code format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.7.9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 power reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 gain configuration flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 spi interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.1 write a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
revision 1.0 february 2011 ? semtech www.semtech.com /products/ page 3 section page table of content advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition 9.2.2 read a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.3 multiple bytes write/read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 adc samples reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3.1 sample shift mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3.2 combined data ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.4 chip start detection with slave select pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.5 improving noise immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 register memory map and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2.1 rc register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2.2 gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2.3 software reset register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.4 zadc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.5 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 typical performances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1.1 switched capacitor principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2 frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.3 linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.3.1 integral non-linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.3.2 differential non-linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.4 noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.5 gain error and offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.6 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 f amily o verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12 comparison table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 comparison by package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 m echanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15 how to evaluate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16 package outline drawing: mlpq-w16-4x4-ep1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17 land pattern drawing: mlpq-w16-4x4-ep1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18 tape and reel specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
www.semtech.com page 4 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech electrical specifications 1 absolute maximum ratings note the absolute maximum ratings, in table below, are stress ratings only. functional operation of the device at conditions ot her than those indicated in the operating conditions sections of this specificatio n is not implied. exposure to the absolute maximum ratings, wh ere different to the operating conditions, for an extended period may reduce the reliability or useful lifetime of the product. table 1. absolute maximum ratings parameter symbol condition min max units power supply v batt v ss - 0.3 6.5 v storage temperature t store -55 150 c temperature under bias t bias -40 140 c input voltage v inabs all inputs v ss - 300 v batt + 300 mv peak reflow temperature t pkg 260 c esd conditions esd hbm human body model esd 2000 v latchup 100 ma
www.semtech.com page 5 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 2 operating conditions unless otherwise specified: v ref,adc = v batt , v in = 0v, over-sampling frequency f s = 250 khz, pga3 on with gain = 1 , pga1&pga2 off , offsets gdoff2 = gdoff3 = 0. power operation: normal ( ibampadc[1:0] = ibamppga[1:0] = '01'). for resolution n = 12 bits: osr = 32 and n elconv = 4. for resolution n = 16 bits: osr = 256 and n elconv = 2. bandgap chopped at n elconv rate. if v batt < 3v, charge pump is forced on. if v batt > 3v, charge pump is forced off. . table 2. operating conditions limits parameter symbol comment/condition min typ max unit power supply v batt 2.4 5.5 v operating temperature t op -40 125 c table 3. electrical characteristics parameter symbol comment/condition min typ max unit current consumption 1 active current, 5.5v i op55 16 b @ 250 sample/s adc, fs = 125 khz 250 300 a 16 b @ 1ksample/s pga3 + adc, fs = 500 khz 650 850 16 b + gain 1000 @ 1ksample/s pga3,2,1 + adc, fs = 500 khz 1000 1250 active current, 3.3v i op33 16 b @ 250 sample/s adc, fs = 125 khz 150 a 16 b @ 1 ksample/s pga3 + adc, fs = 500 khz 500 16 b + gain 1000 @ 1ksample/s pga3,2,1 + adc, fs = 500 khz 830 sleep current i sleep @25c 150 250 na up to 85c 200 @125c 250 time base max adc over-sampling frequency f smax @25c 425 500 575 khz adc over-sampling frequency drift f st 0.15 % / c digital i/o input logic high v ih 0.7 v batt input logic low v il 0.3 v batt output logic high v oh i oh < 4 ma v batt -0.4 v output logic low v ol i ol < 4 ma 0.4 v leakages currents
www.semtech.com page 6 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech input leakage current i leakin digital input mode, no pull-up or pull-down -100 100 na vref: internal bandgap reference absolute output voltage v bg v batt > 3v 1.19 1.22 1.25 v variation over temperature v bgt v batt > 3v, over temperature -1.5 +1.5 % total output noise v bgn v batt > 3v 1 mvrms 1. the device can be operated in either active or sleep states. the sleep state is complete shutdown, but the active state can h ave a variety of different current consumptions depending on the settings. some examples are given here: the sleep state is the default state af ter power-on-reset. the chip can then be placed into an active state after a valid i2c communication is received. table 4. zoomingadc specifications parameter symbol condition min typ max unit analog input characteristics differential input voltage range v in = v inp -v inn gain=1, osr=32, v ref =5v. note 1 -2.42 +2.42 v gain=100, osr=32, v ref =5v -24.2 +24.2 mv gain=1000, osr=32, v ref =5v -2.42 +2.42 mv programmable gain amplifier total pga gain gd tot note 1 1/12 1000 v/v pga1 gain gd 1 (see table 10, page 22 )1 10v/v pga2 gain gd 2 (see table 11, page 22 )1 10v/v pga3 gain gd 3 step = 1/12 v/v (see table 12, page 22 ) 1/12 127/12 v/v gain settings precision (each stage) gain 1 -3 0.5 +3 % gain temperature dependence 5 ppm / c pga2 offset gd off2 step = 0.2 v/v (see table 11, page 22 ) -1 +1 v/v pga3 offset gd off3 step = 1/12 v/v (see table 12, page 22 ) -63/12 +63/12 v/v offset settings precision (pga2 or pga3) note 2 -3 0.5 +3 % offset temperature dependence 5 ppm / c input impedance on adc z inadc 500 k input impedance on pga1 (see section 11.1, page 49 ) z inpga1 gain = 1. note 3 900 1150 k gain = 10. note 3 250 350 k input impedance on pga2 z inpga2 gain = 1. note 3 500 1000 k gain = 10. note 3 125 270 k input impedance on pga3 z inpga3 gain = 1. note 3 500 780 k gain = 10. note 3 125 190 k table 3. electrical characteristics parameter symbol comment/condition min typ max unit
www.semtech.com page 7 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech (1) gain defined as overall pga gain gdtot = gd1 x gd2 x gd3 . maximum input voltage is given by: v in,max = ( v ref / 2) ( osr / osr +1). (2) offset due to tolerance on gdoff2 or gdoff3 setting. for small intrinsic offset, use only adc and pga1 . (3) measured with block connected to inputs through amux block. normalized input sampling frequency for input impedance is f s = 500 khz ( f s max, worst case). this figure must be multiplied by 2 for f s = 250 khz, 4 for f s = 125 khz. input impedance is proportional to 1/ f s . (4) figure independent from gain and sampling frequency. f s . the effective output noise is re duced by the over-sampling ratio (5) resolution is given by n = 2 log2( osr ) + log2( n elconv ). osr can be set between 8 and 1024, in powers of 2. n elconv can be set to 1, 2, 4 or 8. (6) if a ramp signal is applied to the input, all digital codes appear in the resulting adc output data. (7) gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function (with the offset error removed). (8) offset error is defined as the output code error for a ze ro volt input (ideally, output code = 0). for 1 lsb offset, n elconv must be at least 2. output rms noise per over-sample pga1. note 4 205 v pga2. note 4 340 v pga3. note 4 365 v adc static performances resolution (no missing codes) n note 5 note 6 616bits gain error note 7 0.15 % offset error n = 16 bits. note 8 1lsb integral non-linearity inl resolution n = 12 bits. note 9 0.6 lsb resolution n = 16 bits. note 9 1.5 lsb differential non-linearity dnl resolution n = 12 bits. note 10 0.5 lsb resolution n = 16 bits. note 10 0.5 lsb power supply rejection ratio dc psrr v batt = 5v +/- 0.3v. note 11 78 db v batt = 3v +/- 0.3v. note 11 72 db adc dynamic performances conversion time t conv n = 12 bits. note 12 133 fs cycles n = 16 bits. note 12 517 fs cycles throughput rate (continuous mode) 1/t conv n = 12 bits, fs = 250 khz 1.88 ksps n = 16 bits, fs = 250 khz 0.483 ksps pga stabilization delay note 13 (see table 11, page 22 ) osr fs cycles zadc analog quiescent current adc only consumption i q v batt = 5.5v/3.3v 285/210 a pga1 consumption v batt = 5.5v/3.3v 104/80 a pga2 consumption v batt = 5.5v/3.3v 67/59 a pga3 consumption v batt = 5.5v/3.3v 98/91 a analog power dissipation: all pgas & adc active normal power mode v batt = 5.5v/3.3v. note 14 4.0/2.0 mw 3/4 power reduction mode v batt = 5.5v/3.3v. note 15 3.2/1.6 mw 1/2 power reduction mode v batt = 5.5v/3.3v. note 16 2.4/1.1 mw 1/4 power reduction mode v batt = 5.5v/3.3v. note 17 1.5/0.7 mw table 4. zoomingadc specifications parameter symbol condition min typ max unit
www.semtech.com page 8 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech (9) inl defined as the deviation of the dc transfer curve of each individual code from the best-f it straight line. this specific ation holds over the full scale. (10) dnl is defined as the difference (in lsb) between the idea l (1 lsb) and measured code transitions for successive codes. (11) values for gain = 1. psrr is defined as the amount of change in the adc output value as the power supply voltage changes. (12) conversion time is given by: t conv = ( n elconv ( osr + 1) + 1) / f s . osr can be set between 8 and 1024, in powers of 2. n elconv can be set to 1, 2, 4 or 8. (13) pgas are reset after each writing operation to registers regaccfg1-5 , corresponding to change of configuration or input switching. the adc should be started only some delay after a change of pga config uration through these registers. delay between change of configur a- tion of pga or input channel switching and adc start should be equivalent to osr (bet ween 8 and 1024) number of cycles. this is done by writing bit start several cycles after pga settings modification or channel switching. this delay does not apply to conversions made with- out the pgas . (14) nominal (maximum) bias currents in pgas and adc , i.e. ibamppga[1:0] = '11' and ibampadc[1:0] = '11'. (15) bias currents in pgas and adc set to 3/4 of nominal values, i.e. ibamppga[1:0] = '10', ibampadc[1:0] = '10'. (16) bias currents in pgas and adc set to 1/2 of nominal values, i.e. ibamppga[1:0] = '01', ibampadc[1:0] = '01'. (17) bias currents in pgas and adc set to 1/4 of nominal values, i.e. ibamppga[1:0] = '00', ibampadc[1:0] = '00'.
www.semtech.com page 9 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 2.1 timing characteristics (18) the ready pulse indicates end of conversion. this is a positi ve pulse of duration equal to one cycle of the adc sampling ra te in continu- ous mode. see also figure 15, page 30 for data conversion waveforms. 2.1.1 por timings the slave select pin (ss ) can be used to detect the effective start of the device. see section 9.4, page 42 for functional descriptions. the spi interface can be accessed as soon as the ss pin (slave) is set to output as illustrated on figure 2 . table 5. general timings parameter symbol comment/condition min typ max unit adc interrupt (ready) timing specifications ready pulse width t irq note 18 11/fs startup times startup sequence time at por t startup 800 s time to enable rc from sleep after a spi command t rcen 100 450 s effective start t start_spi 250 s figure 1. spi master detecting start sequence through slave select pin figure 2. slave select pin and power-on-reset timings master sx872xs slave ss ss mss sss por self calibration rc disabling t por t rcen t rcen rc enabling rc enabling t start_spi startup sequence wake-up sequence mss direction por sss output input sx status sleep t startup
www.semtech.com page 10 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 2.1.2 spi interface timings 2.1.3 spi timing diagram parameter symbol min typ max units ss to sclk edge t sssc 30 ns sclk period t sc 250 500 ns sclk low pulse width t scl 100 ns sclk high pulse width t sch 100 ns data output valid after sclk edge t dv 125 200 ns data input setup time before sclk edge t ds 0ns data input hold time after sclk edge t dh 100 250 ns ss high after sclk edge t sssc 0ns ss high to miso high impedance t ssd 30 ns figure 3. spi timing diagram t sch t scl t sc mosi miso sclk ss t sssc t scss t ds t dh t dv t ssd
www.semtech.com page 11 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech circuit description 3 pin configuration 4 marking information nnnnn = part number yyww = date code 1 xxxxx = semtech lot number xxxxx 1.date codes and lot numbers starting with the e character are used for engineering samples ac5 vbatt vss ac7 SX8724S (top view) ac2 vpump sclk mosi ready ac3 ac6 ac4 1 2 3 4 56 78 9 10 11 12 13 14 15 16 d0 miso/ready ss d1 8724s yyww xxxxx xxxxx
www.semtech.com page 12 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 5 pin description note the bottom pad is internally connected to vss . it should also be connected to vss on pcb to reduce noise and improve thermal behavior. pin name type function 1 ac3 analog input differential sensor input in conjunction with ac2 2 ac6 analog input differential sensor input in conjunction with ac7 3 ac7 analog input differential sensor input in conjunction with ac6 4 ac4 analog input differential sensor input in conjunction with ac5 5 ac5 analog input differential sensor input in conjunction with ac4 6 vbatt power input 2.4v to 5.5v power supply 7 vss power input chip ground 8 ready digital output data ready (active high). conversion complete flag. 9d1 digital io digital output sensor drive (v batt or v ss ) analog v ref input in optional operating mode 10 ss digital input slave select (active low). this pin is set as output low during the por sequence. 11 miso/ready digital output serial data out (master input, slave ou tput), or data out combined with data ready (active low when data ready function enabled). 12 d0 digital io digital output sensor drive (v batt or v ss ) analog v ref output in optional operating mode 13 mosi digital input serial data in (master output, slave input) 14 sclk digital input serial clock from the master. 15 vpump power io charge pump output. rais es adc supply above v batt if v batt supply is too low. recommended range for capacitor is 1nf to 10 nf. connect the capacitor to ground. 16 ac2 analog input differential sensor input in conjunction with ac3
www.semtech.com page 13 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 6 general description the SX8724S is a complete low-power acquisition path wi th programmable gain, acquisition speed and resolution. 6.1 bloc diagram 6.2 vref the internally generated v ref is a trimmed bandgap reference with a nomi nal value of 1.22v that provides a stable voltage reference for the zoomingadc . this reference voltage is directly connected to on e of the zoomingadc reference multiplexer inputs. the bandgap voltage stability is only guaranteed for v batt voltages of 3v and above. as v batt drops down to 2.4v, the bandgap voltage could reduce by up to 50mv. the bandgap has relatively weak output drive so it is reco mmended that if the bandgap is required as a signal input then pga1 must be enabled with gain = 1. 6.3 gpio the gpio block is a multipurpose 2 bit input/output port. in addition to digital behavior, d0 and d1 pins can be programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an external figure 4. SX8724S bloc diagram ac0 signal mux + - + - ref mux ready ac3 ac2 ac1 pga adc v ref + - zoomingadc tm vpump vbatt d1/ref in d0/ref out SX8724S vss control logic gpio charge pump 4mhz osc ac5 ac4 ac7 ac6 mosi miso/ready spi sclk ss
www.semtech.com page 14 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech reference voltage (for further details see figure 7 , figure 8 , figure 9 and figure 10 ). each port terminal can be individually selected as digital input or output. the direction of each bit within the gpio block (input only or input/output) can be individually set using the bits of the regout (address 0x40) register. if d[x]dir = 1, both the input and output buffer are active on the corresponding gpio block pin. if d[x]dir = 0, the corresponding gpio block pin is an input only and the ou tput buffer is in high impedance. after power on reset the gpio block pins are in input/output mode ( d[x]dir are reset to 1). the input values of gpio block are available in regin (address 0x41) register (read only). reading is always direct - there is no debounce function in the gpio block. in case of possible noise on input signals, an external hardware filter has to be realized. the input buffer is also active when the gpio block is defined as output an d the effective value on the pin can be read back. data stored in the lsb bits of regout register are outputted at gpio block if d[x]dir= 1 . the default values after power on reset is low (0). the digital pins are able to deliver a driving current up to 8 ma. when the bits vrefd0out and vrefd1in in the regmode (address 0x70) register are set to 1 the d0 and d1 pins digital behavior are automatically bypassed in order to either input or output the voltage reference signals. figure 5. gpio bloc diagram regout[4] regout[5] regout[0] regin[0] regout [1] regin [1] v bg + - d1/vref d0/vref regmode [0] 0 1 regmode[1] 0 1 0 1 zoomingadc in out v ref internal bandgap reference 1.22v
www.semtech.com page 15 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 6.3.1 optional operating mode: external vref d0 and d1 are multi-functional pins with the followin g functions in different operating modes (see regmode register for control settings): this allows external monitoring of the internal bandgap refe rence or the ability to use an external reference input for the adc , or the option to filter the internal v ref output before feeding back as v ref,adc input. the internally generated v ref is a trimmed as adc reference with a nomi nal value of 1.22v. when using an external v ref,adc input, it may have any value between 0v and v batt . simply substitute the external value for 1.22 v in the adc conversion calculations. figure 7. d0 and d1 are digital inputs / outputs figur e 8. d1 is reference voltage input and d0 is digital input / output figure 9. d1 is digital input / output and d0 reference voltage output figure 10. d0 is reference voltage output and d1 is reference voltage input + - d1/vref in d0/vref out regmode[0] = 0 0 1 regmode[1] = 0 0 1 0 1 gpio zoomingadc gpio internal bandgap reference v bg v ref + - d1/vref in d0/vref out regmode[0] = 1 0 1 regmode[1] = 0 0 1 0 1 gpio zoomingadc gpio internal bandgap reference v ref + - d1/vref in d0/vref out regmode[0] = 0 0 1 regmode[1] = 1 0 1 0 1 gpio zoomingadc gpio internal bandgap reference v bg v ref + - d1/vref in d0/vref out regmode[0] = 1 0 1 regmode[1] = 1 0 1 0 1 gpio zoomingadc gpio internal bandgap reference v bg v ref
www.semtech.com page 16 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 6.4 charge pump this block generates a supply voltage able to power the an alog switch drive levels on the chip higher than v batt if necessary. if v batt voltage drops below 3v then the block should be activated. if v batt voltage is greater than 3v then v batt may be switched straight through to the vpump output. if the charge pump is not activated then v pump = v batt. if control input bit multforceoff = 1 in regmode (address 0x70) register then th e charge pump is disabled and v batt is permanently connected to vpump output. if control input bit multforceon = 1 in regmode register then the charge pump is permanently enabled. this overrides multforceoff bit in regmode register. an external capacitor is required on vpump pin. this capacitor should be large enough to ensure that generated voltage is smooth enough to avoid affect ing conversion accuracy but not so large that it gives an unacceptable settling time. a recommended value is around 2.2nf. 6.5 rc oscillator this block provides the master clock reference for the chip. it produces a clock at 4 mhz which is divided internally in order to generate the clock sour ces needed by the other blocks. the oscillator technique is a low power relaxation design an d it is designed to vary as little as possible over temperature and supply voltage. this oscillator is trimmed at manufacture chip test. the rc oscillator will start up after a chip reset to allow the trimming values to be read and calibration registers. once this has been done, the oscillator will be shut down and the chip will enter a sleep state while waiting for a spi communication. the worst case duration from reset ( or por ) to the sleep state is 800us. 6.5.1 wake-up from sleep when the device is in sleep state, the rc oscillator will start up after a communic ation. the start up sequence for the rc oscillator is 450us in worst case. during this time, the internal blocs using the rc can not be used: no adc conversion can be started.
www.semtech.com page 17 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 7 zoomingadc 7.1 overview the zoomingadc is a complete and versatile low-power analog fr ont-end interface typically intended for sensing applications. in the following text the zoomingadc will be referred as zadc . the key features of the zadc are: programmable 6 to 16-bit dy namic range over-sampled adc flexible gain programming between 1/12 and 1000 flexible and large range offset compensation differential or single-ended input 2-channel differential reference inputs power saving modes the total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an over sampled a/d converter. the reference voltage can be selected on tw o different channels. two offset compensation amplifiers allow for a wide offset compensation range. the programmable gain and offset allow the a pplication to zoom in on a small portion of the reference voltage defined input range. 7.1.1 acquisition chain figure 11, page 17 shows the general block diagra m of the acquisition chain ( ac ). a control block (not shown in figure 11 ) manages all communications with the spi peripheral . the clocking is derived from the internal 4 mhz oscillator. analog inputs can be selected throug h an 8 input multiplexer, while refe rence input is selected between two differential channels. it should however be noted that only 7 acquisition channels (including the v ref ) are available when configured as single ended since the input amplifier is always operating in differential mode with both positive and negative input selected through the multiplexer. figure 11. zadc general functional block diagram pga1 pga2 pga3 adc vin vin vin vin voff voff vref amux analog inputs vmux reference inputs v in v d1 v d2 v in,adc v ref,adc v ss v ref ac 2 ac 3 ac 4 ac 5 ac 6 ac 7 v ss v batt v ss v ref analog zoom s
www.semtech.com page 18 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech the core of the zooming section is made of three differential programmable amplifiers ( pga ). after selection of an input and reference signals v in and v ref,adc combination, the input voltage is modulated and amplified through stages 1 to 3. fine gain programming up to 1'000 v/v is possible. in addition, th e last two stages provide programmable offset. each amplif ier can be bypassed if needed. the output of the cascade of pga is directly fed to the analog-to-digital converter ( adc ), which converts the signal v in,adc into digital. like most adcs intended for instrumentation or sensing applications, the zoomingadc tm is an over-sampled converter 1 . the adc is a so-called incremental converter; with bipolar operation (the adc accepts both positive and negative differential input voltages). in first approximation, the adc output result relative to full-scale ( fs ) delivers the quantity: in two's complement (see equation 18 and equation 19, page 30 for details). the output code out adc is - fs / 2 to + fs / 2 for v in,adc = -v ref,adc / 2 to + v ref,adc / 2 respectively. as will be shown, v in,adc is related to input voltage v in by the relationship: where gd tot is the total pga gain, gd offtot is the total magnitude of pga offset and s is the sign of the offset (see table 8, page 21 ). 7.1.2 programmable gain amplifiers as seen in figure 11, page 17 , the zooming function is implemented with three programmable gain amplifiers ( pga ). these are: pga1 : coarse gain tuning pga2 : medium gain and offset tuning pga3 : fine gain and offset tuning. should be set on for high linearity data acquisition all gain and offset settings are realized with rati os of capacitors. the user has control over each pga activation and gain, as well as the offset of stages 2 an d 3. these functions are examined hereafter. 1. over-sampled converters are operated with a sampling frequency f s much higher than the input si gnal's nyquist rate (typically f s is 20- 1'000 times the input signal bandwi dth). the sampling frequency to throughput ra tio is large (typically 10-500). these converte rs include digital decimation filtering. they are mainly used for high resolution, and/or low-to-medium speed applications. equation 1 equation 2 2 / 2 / , ref adc in adc v v fs out ? ] [ , v v s gdoff v gd v ref tot in tot adc in ? ? ? ? =
www.semtech.com page 19 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 7.1.3 pga & adc enabling depending on the application objectives, the user may enable or bypass each pga stage. this is done according to the word enable and the coding given in table 6 . to reduce power dissipation, the adc can also be inactivated while idle. 7.2 zoomingadc registers the system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain ( regaccfg0 to regaccfg5 ), and two registers are used to store the outp ut code of the analog-to-digital conversion ( regacoutmsb & lsb ). (r = read; w = write; rw = read & write) (1) out : (r) digital output code of the analog-to-digital converter. ( msb = out[15] ) (2) start : (w) setting this bit triggers a single conversion (after the current one is finished). this bit always reads back 0. table 6. adc and pga enabling enable (regaccfg1[3:0]) block xxx0 xxx1 adc disabled adc enabled xx0x xx1x pga1 disabled pga1 enabled x0xx x1xx pga2 disabled pga2 enabled 0xxx 1xxx pga3 disabled pga3 enabled table 7. registers to configure the acquisition chain (ac) and to store the analog-to-digital conversion (adc) result register name bit position 76543210 regacoutlsb out [7:0] note 1 regacoutms b out [15:8] regaccfg0 default values: start 0, note 2 setnelconv 01, note 3 setosr 010, note 4 continuous 0, note 5 sampleshiften 0, note 6 regaccfg1 default value: ibampadc 11, note 7 ibamppga 11, note 8 enable 0000, note 9 regaccfg2 default value: setfs 00, note 10 pga2gain 00, note 12 pga2offset 0000, note 14 regaccfg3 default value: pga1gain 0, note 11 pga3gain 0001100, note 13 regaccfg4 default value: datareadyen 0, note 15 pga3offset 0000000, note 16 regaccfg5 default value: busy 0, note 17 def 0, note 18 amux 00000, note 19 vmux 0, note 20
www.semtech.com page 20 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech (3) setnelconv : (rw) sets the number of elementary conversions to 2 (setnelconv[1:0]) . to compensate for offsets, the input signal is chopped between elementary conversions (1,2,4,8). (4) setosr : (rw) sets the over-sampling rate ( osr ) of an elementary conversion to 2 (3+setosr[2:0]) . osr = 8, 16, 32, ..., 512, 1024. (5) continuous : (rw) setting this bit starts a conversion. when this bis is 1, a new conversion will automatically begin directly when the pr evi- ous one is finished. (6) sampleshiften : (rw) the 16-bit samples can be directly shifted out though the spi interface by the master when a conversion is done. (7) ibampadc : (rw) sets the bias current in the adc to 0.25 x (1+ ibampadc[1:0] ) of the normal operation current (25, 50, 75 or 100% of nom- inal current). to be used for low-power, low-speed operation. (8) ibamppga : (rw) sets the bias current in the pgas to 0.25 x (1+ ibamppga[1:0] ) of the normal operation curren t (25, 50, 75 or 100% of nom- inal current). to be used for low-power, low-speed operation. (9) enable : (rw) enables the adc modulator (bit 0) and the different stages of the pgas ( pgai by bit i=1,2,3). pga stages that are disabled are bypassed. (10) setfs : (rw) these bits set the over sampling frequency of the acquis ition chain. expressed as a frac tion of the oscillator frequency , the sampling frequency is given as: 11 ' 500 khz, 10 ' 250 khz, 01 ' 125 khz, 00 ' 62.5 khz. (11) pga1gain : (rw) sets the gain of the first stage: 0 ' 1, 1 ' 10. (12) pga2gain : (rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10. (13) pga3gain : (rw) sets the gain of the third stage to pga3gain[6:0] 1/12. (14) pga2offset : (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. the msb gives the sign (0 positive, 1 neg- ative); amplitude is coded with the bits pga2offset[5:0]. (15) datareadyen : (rw) enables the combined data ready mode with the miso of the spi interface. (16) pga3offset : (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. the msb gives the sign (0 positive, 1 negative); amplitude is coded with the bits pga3offset[5:0] . (17) busy : (r) set to 1 if a conversion is running. (18) def : (w) sets all values to their defaults (pga disabled, amux not changed, vmux not changed, adc enabled, nominal modulator bias cur- rent (100%), 2 elementary conversions, osr = 32, n elconv = 2, fs = 62.5khz) and starts a new conversion without waiting the end of the preceding one. (19) amux (4:0): (rw) amux[4] sets the mode (0 ' differential inputs, 1 ' single ended inputs with a0= common reference) amux[3] sets the sign (0 ' straight, 1' cross) amux[2:0] sets the channel. (20) vmux : (rw) sets the differential reference channel (0 ' v batt , 1 ' v ref ). 7.3 input multiplexers (amux and vmux) the zoomingadc has analog inputs ac0 to ac7 and reference inputs. let us first define the differential input voltage v in and reference voltage v ref,adc respectively as: equation 3 equation 4 ] [ v v v v inn inp in ? = ] [ v v v v refn refp ref ? =
www.semtech.com page 21 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech as shown in table 8 , the inputs can be configured in two wa ys: either as 4 differential channels ( v in1 = ac1 - ac0 ,... , v in4 = ac7 - ac6 ), or ac0 can be used as a common reference, pr oviding 7 signal paths all referred to ac0 . the control word for the analog input selection is amux . notice that the amux bit 4 controls the sign of the input voltage. similarly, the reference voltage is chosen among two differential channels ( v ref = v batt -v ss , v ref = v bg - v ss or v ref = v ref,in - v ss ) as shown in table 9 . the selection bit is vmux . the reference inputs v refp and v refn (common-mode) can be up to the power supply range. 7.4 first stage programmabl e gain amplifier (pga1) the first stage can have a buffer function (unity gain) or provide a gain of 10 (see table 10 ). the voltage v d1 at the output of pga1 is: table 8. analog input selection amux (regaccfg5[5:1]) v inp v inn amux (regaccfg5[5:1]) v inp v inn sign s = 1 sign s = -1 00x00 ac1(v ref )ac0(v ss ) 01x00 ac1(v ss )ac0(v ref ) 00x01 ac3 ac2 01x01 ac2 ac3 00x10 ac5 ac4 01x10 ac4 ac5 00x11 ac7 ac6 01x11 ac6 ac7 10000 ac0(v ss ) ac0(v ss ) 11000 ac0(v ss ) ac0(v ss ) 10001 ac1(v ref ) 11001 ac1(v ref ) 10010 ac2 11010 ac2 10011 ac3 11011 ac3 10100 ac4 11100 ac4 10101 ac5 11101 ac5 10110 ac6 11110 ac6 10111 ac7 11111 ac7 table 9. analog reference input selection vmux (regaccfg5[0]) v refp v refn 0v ref = v batt v ss 1 v ref = v bg or v ref,in 1 1. external voltage reference on d1 gpio pin. see section 6.3 on page 13 about gpio and regmode[0x70] on page 48. v ss equation 5 ] [ 1 1 v v gd v in d ? =
www.semtech.com page 22 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech where gd 1 is the gain of pga1 (in v/v) controlled with the pga1gain bit. 7.5 second stage programma ble gain amplifier (pga2) the second pga has a finer gain and offset tuning capability, as shown in table 11 . the v d2 voltage at the output of pga2 is given by: where gd 2 and gd off2 are respectively the gain and offset of pga2 (in v/v). these are controlled with the words pga2gain[1:0] and pga2offset[3:0] . 7.6 third stage programmabl e gain amplifier (pga3) the finest gain and offset tuning is performed with the third and last pga stage, according to the coding of table 12 . table 10. pga1 gain settings pga1gain bit (regaccfg3[7]) pga1 gain [v/v] gd 1 [v/v] 01 110 equation 6 table 11. pga2 gain and offset settings pga2gain bit field (regaccfg2[5:4]) pga2 gain [v/v] gd 2 [v/v] pga2offset bit field (regaccfg2[3:0]) pga2 offset gd off2 [v/v] 00 1 0000 0 01 2 0001 +0.2 10 5 0010 +0.4 11 10 0011 +0.6 0100 +0.8 0101 +1 1000 0 1001 -0.2 1010 -0.4 1011 -0.6 1100 -0.8 1101 -1.0 table 12. pga3 gain and offset settings pga3gain bit field (regaccfg3[6:0]) pga3 gain gd 3 [v/v] pga3offset bit field (regaccfg4[6:0]) pga3 offset gd off3 [v/v] 0000000 0 0000000 0 0000001 1/12 (=0.083) 0000001 +1/12 (=0.083) ] [ 2 1 2 2 v v s gdoff v gd v ref d d ? ? ? ? =
www.semtech.com page 23 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech the output of pga3 is also the input of the adc . thus, similarly to pga2 , we find that the voltage entering the adc is given by: where gd 3 and gd off3 are respectively the gain and offset of pga3 (in v/v). the control words are pga3gain[6:0] and pga3offset[6:0] . to remain within the signal compliance of the pga stages (no saturation), the condition: must be verified. ... ... ... 0000110 6/12 0010000 +16/12 ... ... ... ... 0001100 12/12 0100000 32/12 0010000 16/12 ... ... ... ... 0111111 +63/12 (=+5.25) 0100000 32/12 1000000 0 ... ... 1000001 -1/12 (=-0.083) 1000000 64/12 1000010 -2/12 ... ... ... ... 1111111 127/12 (=10.58) 1010000 -16/12 ... ... 1100000 -32/12 ... ... 1111111 -63/12 (=-5.25) equation 7 equation 8 table 12. pga3 gain and offset settings pga3gain bit field (regaccfg3[6:0]) pga3 gain gd 3 [v/v] pga3offset bit field (regaccfg4[6:0]) pga3 offset gd off3 [v/v] ] [ 3 2 3 , v v s gdoff v gd v ref d adc in ? ? ? ? = 2 , , 2 1 batt d d in v v v v <
www.semtech.com page 24 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech to remain within the signal compliance of the adc (no saturation), the condition: must be verified. finally, combining equation 5 to equation 7 for the three pga stages, the input voltage v in,adc of the adc is related to v in by: where the total pga gain is defined as: and the total pga offset is: equation 9 equation 10 equation 11 equation 12 ? ? ? ? ? ? ? ? ? ? ? ? ? < osr osr v v ref adc in 1 2 , ] [ , v v s gdoff v gd v ref tot in tot adc in ? ? ? ? = 1 2 3 gd gd gd gd tot ? ? 2 3 3 gdoff gd gdoff gdoff tot ?
www.semtech.com page 25 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 7.7 analog-to-digital converter (adc) the main performance characteristics of the adc (resolution, conversion time, etc.) are determined by three programmable parameters. the setting of these parameters and the resulting performances are described later. fs :over-sampling frequency osr :over-sampling ratio n elconv : number of elementary conversions 7.7.1 conversion sequence a conversion is started each time the bit start or the def bit is set. as depicted in figure 12 , a complete analog-to- digital conversion sequence is made of a set of n elconv elementary incremental conversions and a final quantization step. each elementary conversion is made of ( osr +1) over-sampling periods ts =1/ fs , i.e.: the result is the mean of the elementary conversion result s. an important feature is that the elementary conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the output code. thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if n elconv >= 2). a few additional clock cycles are also requ ired to initiate and end the conversion properly. equation 13 figure 12. analog-to-digital conversion sequence note the internal bandgap reference state may be forced high or low, or may be set to toggle during conversion at either the same rate or half the rate of the elementary conversion. this may be useful to help eliminate bandgap related internal offset voltage and 1/ fs noise. ] [ / ) 1 ( s f osr t s elconv + = init elementary conversion elementary conversion elementary conversion elementary conversion end conversion index offset 12 n elconv -1 n elconv conversion result +- +- t conv
www.semtech.com page 26 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 7.7.2 over-sampling frequency (fs) the word setfs[1:0] (see table 13 ) is used to select the over-sampling frequency fs . the over-sampling frequency is derived from the 4mhz oscillator clock. 7.7.3 over-sampling ratio (osr) the over-sampling ratio ( osr ) defines the number of integration cycles per elementary conversion. its value is set with the word setosr[2:0] in power of 2 steps (see table 14 ) given by: 7.7.4 number of elementary conversions (nelconv) as mentioned previously, the whole conversion sequence is made of a set of n elconv elementary incremental conversions. this number is set with the word setnelconv[1:0] in power of 2 steps (see table 15 ) given by: table 13. sampling frequency settings setfs bit field (regaccfg2[7:6]) over-sampling frequency fs [hz] 00 62.5 khz 01 125 khz 10 250 khz 11 500 khz equation 14 table 14. over-sampling ratio settings setosr[2:0] (regaccfg[4:2]) over-sampling ratio osr [-] 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 equation 15 ] [ 2 0] : setosr[2 3 ? = + osr ] [ 2 0] : [1 setnelconv ? = elconv n
www.semtech.com page 27 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech as already mentioned, n elconv must be equal or greater than 2 to reduce internal amplifier offsets. 7.7.5 resolution the theoretical resolution of the adc , without considering thermal noise, is given by: using look-up table 16 or the graph plotted in figure 13 , resolution can be set between 6 and 16 bits. notice that, because of 16-bit register use for the adc output, practical resolution is limited to 16 bits , i.e. n = 16. even if the table 15. number of elementary conversion setosr[2:0] (regaccfg[4:2]) # of elementary conversion n elconv [-] 00 1 01 2 10 4 11 8 equation 16 figure 13. resolution vs. setosr[2:0] and setnelconv[2:0] ] [ ) ( log ) ( log 2 2 2 bit n osr n elconv + ? = 14.0 12.0 8.0 6.0 4.0 000 010 100 resolution - n[bits] setosr[2:0] 16.0 10.0 00 01 10 11 001 011 101 110 111 setnelconv[1:0]
www.semtech.com page 28 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech resolution is truncated to 16 bit by the output register size, it may make sense to set osr and n elconv to higher values in order to reduce the influence of the thermal no ise in the pga. 7.7.6 conversion time & throughput as explained in figure 13 , conversion time is given by: and throughput is then simply 1/ t conv . for example, consider an over-sampling ratio of 256, 2 elementary conversions, and a sampling frequency of 500 khz ( setosr = "101", setnelconv = "01" and setfs = "00"). in this case, using table 17 , the conversion time is 515 sampling periods, or 1.03ms. th is corresponds to a throughput of 971hz in continuous-time mode. the plot of figure 14 illustrates the classic trade-off betw een resolution and conversion time. table 16. resolution 1 vs. setosr and setnelconv settings 1. in shaded area, the resolution is truncate d to 16 bits due to output register size rega- cout[15:0] setosr control bits setnelconv control bits 00 01 10 11 000 6789 001 891011 010 10 11 12 13 011 12 13 14 15 100 14 15 16 16 101 16 16 16 16 110 16 16 16 16 111 16 16 16 16 equation 17 table 17. normalized conversion time (tconv x fs) vs. setosr and setnelconv settings 1 setosr bits osr setnelconv control bits n elconv 00 1 01 2 10 4 11 8 000 10 19 37 73 001 18 35 69 137 010 34 67 133 265 011 66 131 261 521 ] [ / ) 1 ) 1 ( ( s f osr n t s elconv conv + + ? =
www.semtech.com page 29 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 7.7.7 continuous-time vs. on-request conversion the adc can be operated in two distinct modes: "continuou s-time" and "on-request" modes (selected using the bit continuous ). 100 130 259 517 1033 101 258 515 1029 2057 110 514 1027 2053 4105 111 1026 2051 4101 8201 1. normalized to sampling period 1/fs figure 14. resolution vs. normalized 1 conversion time for different setnelconv[1:0] 1. normalized conversion time - t conv x fs table 17. normalized conversion time (tconv x fs) vs. setosr and setnelconv settings 1 setosr bits osr setnelconv control bits n elconv 00 1 01 2 10 4 11 8 14.0 12.0 8.0 6.0 4.0 10 100 1000 10000 resolution - n[bits] normalized conversion time ? tconv x fs [-] 16.0 10.0 00 01 10 11
www.semtech.com page 30 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech in "continuous-time" mode, the input signal is repeatedly converted into digital. after a conversion is finished, a new one is automatically initiated. the new value is then writ ten in the result register, and the corresponding internal trigger pulse is generated. this operation is sketched in figure 15 . the conversion time in this case is defined as t conv . in the "on-request" mode, the internal be havior of the converter is the same as in the "continuous-time" mode, but the conversion is initiated on user request (with the start bit). as shown in figure 16 , the conversion time is also t conv . 7.7.8 output code format the adc output code is a 16-bit word in two's complement format (see table 18 ). for input voltages outside the range, the output code is saturated to the cl osest full-scale value (i.e. 0x7fff or 0x 8000). for resolutions smaller than 16 bits, the non-significant bits are forced to the values shown in table 19 . the output code, expressed in lsbs , corresponds to: recalling equation 10, page 24 , this can be rewritten as: figure 15. adc continuous-time operation figure 16. adc on-request operation equation 18 equation 19 output code regacout[15:0] busy internal trig ready tconv 1/fs output code regacout[15:0] busy internal trig ready tconv start request osr osr v v out ref adc in adc 1 2 , 16 + ? ? = ] [ 1 2 16 lsb osr osr v v s gdoff gd v v out in ref tot tot ref in adc + ? ? ? ? ? ? ? ? ? ? ? ? ? ? =
www.semtech.com page 31 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech where, from equation 11 and equation 12 , the total pga gain and offset are respectively: and: equation 20 equation 21 table 18. basic adc relationships (example for: vref = 5v, osr = 512, n = 16bits) adc input voltage v in,adc % of full scale (fs) output in lsbs hexadecimal output code +2.49505 v +0.5 x fs +2 15 -1 = 32767 7fff +2.49497 v ... +2 15 -2 = 32766 7ffe ... ... ... ... +76.145 v ... +1 0001 0 0 0 0000 -76.145 v ... -1 ffff ... ... ... ... -2.49505 v ... -2 15 -1 = -32767 8001 -2.49513 v -0.5 x fs -2 15 = -32768 8000 table 19. last forced lsbs in conversion output register for resolution settings smaller than 16bits 1 1. (n<16) (regacoutmsb[7 :0] & regacoutlsb[7:0]) setosr[2:0] setnelconv = 00 setnelconv = 01 setnelconv = 10 setnelconv = 11 000 1000000000 100000000 10000000 1000000 001 10000000 1000000 100000 10000 010 100000 10000 1000 100 011 1000 100 10 1 100 10 1 - - 101---- 110---- 111---- 1 2 3 gd gd gd gd tot ? ? = 2 3 3 gdoff gd gdoff gdoff tot ? + =
www.semtech.com page 32 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech the equivalent lsb size at the input of the pga chain is: notice that the input voltage v in,adc of the adc must satisfy the condition: to remain within the adc input range. 7.7.9 power saving modes during low-speed operation, the bias current in the pgas and adc can be programmed to save power using the control words ibamppga[1:0] and ibampadc[1:0] (see table 20 ). if the system is idle, the pgas and adc can even be disabled, thus, reducing power consumption to its mini mum. this can considerably improve battery lifetime. equation 22 equation 23 table 20. adc & pga power saving mo des and maximum sampling frequency ibampadc [1:0] ibamppga [1:0] adc bias current pga bias current max. fs [khz] 00 01 11 1/4 x i adc 1/2 x i adc i adc 125 250 500 00 01 11 1/4 x i pga 1/2 x i pga i pga 125 250 500 ] / [ 1 2 1 v v osr osr gd v lsb tot ref n + ? ? = 1 ) ( 2 1 , + ? ? ? osr osr v v v refn refp adc in
www.semtech.com page 33 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 8 application hints 8.1 power reduction the zoomingadc is particularly well suited for low-powe r applications. when very low power consumption is of primary concern, such as in battery operated systems, se veral parameters can be used to reduce power consumption as follows: operate the acquisition chain wi th a reduced supply voltage v batt . disable the pgas which are not used during anal og-to-digital conversion with enable[3:0] . disable all pgas and the adc when the system is idle and no conversion is performed. use lower bias currents in the pgas and the adc using the control words ibamppga[1:0] and ibampadc[1:0] . reduce sampling frequency. finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed.
www.semtech.com page 34 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 8.2 gain configuration flow the diagram below shows the flow to set the gain of your configuration: figure 17. gain configuration flowchart gain = pga3 enable pga3 gain < 10 ? set gain yes set pga 3 gain enable pga2&3 set pga 2 gain set pga 3 gain set pga 1 gain set pga 2 gain set pga 3 gain gain = pga2 x pga3 gain = pga1 x pga2 x pga3 gain < 100 ? yes no enable pga1,2&3 no end
www.semtech.com page 35 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9 spi interface 9.1 overview the SX8724S serial port interface implements the following: 4-pin interface + options for synchronization to adc sample ready 7-bit target address (max 128 registers) 2 mbps serial clock msb first the serial interface is a slave port for communication with a serial microprocessor bus, allowing the SX8724S to be controlled by an external processor. the serial interface head er must be connected to the host processor, which acts as the master. the serial interface signals are: sclk : s erial cl oc k ss : active low s lave s elect miso / ready : m aster i nput, s lave o utput (data out) and optional active low adc data ready signal. mosi : m aster o utput, s lave i nput. the address and data are transmitted an d received msb first. valid read/write accesses are possible only when ss is active. miso and mosi lines are push-pull pads. as the waveforms illust rate (see below), the slave interface implements a 16-bit shift register. the spi implemented on the SX8724S is set to the common settin g cpol=0 and cpha=0 which means data are sampled on the rising edge of the clock, and shifted on the falling one. the first bit in the serial data is the direction bit. this must be set to '1' for reading, and '0' for writing. the following 7 bits represent the target register address, shifted in msb firs t. the next byte represents register data, shifted in/out msb first. figure 18. example of spi bus with 1 master and 3 slaves master slave 1 slave 2 slave 3 ss ss ss sclk sclk sclk mosi mosi mosi mosi miso miso miso miso sclk ss1 ss2 ss3
www.semtech.com page 36 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9.2 data transmission 9.2.1 write a single register to write to a register, the host must provide the following: 9.2.2 read a single register to read a register from the memory ma p, the host must provide the following: figure 19. spi waveform - write a single register figure 20. spi waveform - read a single register r/w d7 mosi miso ss sclk a6 a5 a4 a3 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d6 d5 d4 d3 d2 d1 d0 write + register address a1 a0 register data r/w d7 read + register address mosi miso ss sclk register data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a6 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0
www.semtech.com page 37 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9.2.3 multiple bytes write/read protocol the spi protocol is designed to be able to do multiple read /write during a transaction. during one single operation, as long as slave select ( ss ) stay asserted, the register address is automatica lly increased to allow sequential read/write (or sequential retrieval of data). the regi ster address will be auto-incremented in multiple read/write commands. between each different operation though the communication should be restarted. figure 21. spi waveform - multiple bytes spi write protocol (2 bytes example) figure 22. spi waveform - multiple bytes spi read protocol (2 bytes example) r/w d7 mosi miso ss sclk a6 a5 a4 a3 a2 12345678910111213141516 d6 d5 d4 d3 d2 d1 d0 write + register address a1 a0 register data[address] d7 17 18 19 20 21 22 23 24 d6 d5 d4 d3 d2 d1 d0 register data[address+1] r/w d7 read + register address mosi miso ss sclk register data 1 12345678910111213141516 a6 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 d7 register data + 1 17 18 19 20 21 22 23 24 d6 d5 d4 d3 d2 d1 d0
www.semtech.com page 38 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9.3 adc samples reading the default spi mode the adc samples must be read with the default spi read sequences described in 9.2. data transmission . the sample shift mode allow to read di rectly the 16-bit conversion result of regacoutlsb[0x50] and regacoutmsb[0x51] without a register read sequence. this mode is described in 9.3.1. sample shift mode . the combined data ready mode is a sample shift mode which combines the adc ready function with the spi miso signal to reduce the number of wires to 4 betwee n the master and the slave. this mode is described in 9.3.2. combined data ready mode section. when the device is in sample shift mode or combined data ready mode, the register reading will give erroneous data. always disable the sample shift mode and combin ed data ready mode to read the registers. figure 23. adc samples reading modes with the spi interface default spi mode sample shift mode enable sample shift mode sampleshiften bit set to ?1? 2 disable sample shift mode sampleshiften bit set to ?0? 4 reset 1 combined data ready with miso mode enable combined data ready mode datareadyen set to 1 3 disable combined data ready datareadyen set to 0 5
www.semtech.com page 39 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9.3.1 sample shift mode if the sampleshiften bit of regaccfg0[0x52] is active, the miso/ready pin is used to shift out adc samples data. these samples are clocked out at falling edge of sclk , msb first (see figure 24 below). as illustrated in figure 25 , five wires are necessary to connect the master in this mode if to be synchronized to the adc end of conversion. when the dataready bit is set to '0', this pin functions as miso only. the combined data ready mode is disabled. 9.3.2 combined data ready mode this combined functionality allows fo r the same control as th e sample shift mode but with fewer pins. samples shifted out (miso) are combined with adc data ready signal (ready ). the datareadyen bit in register regaccfg4[0x56] determines the function of this pin. as illustrated in figure 26 , four wires are necessary to connect figure 24. data retrieval with the sample sh ift mode (combined data ready mode disabled) figure 25. example with two sx872xs slaves mosi miso ss sclk 12345678910111213141516 nop ready d7 d14d13d12d11d10 d6d5d4d3d2d1d0 d9 d8 d15 adc sample msb shifted out (regacoutmsb) adc sample lsb shifted out (regacoutlsb) adc end of conversion, sample ready 1 d15 master sx872xs slave 1 sx872xs slave 2 ss ss sclk sclk mosi mosi mosi miso miso miso sclk ss1 ss2 ready2 ready ready1 ready
www.semtech.com page 40 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech the master in this mode if to be synchr onized to the adc end of conversion. the datareadyen bit modifies only the miso / ready pin functionality. the ready pin functionality remains unaffected. in either mode, the miso /ready pin goes to a high-imp edance state when ss is taken high. when the datareadyen bit in regaccfg4[0x56] register is set to '1', this pin functions as both miso and ready . data are shifted out from this pin, msb first, at the falling edge of sclk . when the datareadymodeen bit is enabled and a new conversion is complete, miso / ready goes low if it is high. if it is already low, then miso / ready goes high and then goes low (see figure 27 below). similar to the ready pin (but with opposite pola rity), a falling edge on the miso/ready pin signals that a new conversion result is ready. after miso / ready goes low, the data can be clocked out by providing 16 clocks pulses on sclk . in order to force miso / ready high (so that miso / ready can be polled for a '0' instead of waiting for a falling edge), a no operation command (nop) or any other co mmand that does not load the data output register can be sent after figure 26. example of 4-wire slave figure 27. data retrieval with the combined data ready mode enabled master sx872xs slave ss sclk mosi mosi miso/ready miso/ready sclk ss mosi miso/ ready ss sclk 12345678910111213141516 nop ready d7 d14d13d12d11d10 d6d5d4d3d2d1d0 d9 d8 d15 adc sample msb shifted out (regacoutmsb) adc sample lsb shifted out (regacoutlsb) adc end of conversion, sample ready
www.semtech.com page 41 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech reading out the data. the miso / ready pin goes high after the first rising edge of sclk after reading the conversion result completely (see figure 28 below). the same condition also applies after a read register comman d. after all the register bits have been read out, the rising edge of sclk forces miso / ready high. the combined data ready mode must not be used with more than one slave. to get the interruption on miso pin, ss should be set to low during all the duration of the combined data ready mode. in combined data ready mode, miso is set to high after the data reception. figure 28. miso/ready forced high after retrieving the conversion result mosi miso/ ready ss sclk 12345678910111213141516 nop ready d7 d14d13d12d11d10 d6d5d4d3d2d1d0 d9 d8 d15 adc sample msb shifted out (regacoutmsb) adc sample lsb shifted out (regacoutlsb) adc end of conversion, sample ready 17 18 19 20 21 22 23 24
www.semtech.com page 42 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9.4 chip start detection with slave select pin at power-up or after a soft reset, ss pin is set to output low during the chip initialization (~250us). if the host ss pin is configured at an input pulled high during the power- up sequence, it can detect the SX8724S effective start. note that if the host pin has a default output high logical level during the power-up or reset sequences this output it will create a short circuit. therefore, a resistor should be put on the line to ensure that no current spikes are generated. the best value for ss resistor should be between 1 k and 10 k . in that range, the current spike is completely avoided and the falling/rising time is ensured. on figure 30 the spi master uses a separate input for startup status reading. the master ss pin is always configured as output for spi slave select. as in the precedent figure, the re sistor on the line to ensure that no current spikes are generated when master and slave ss pins are both configured as ou tputs during a startup sequence. figure 29. set a resistor if the host is a high logical level during the startup or the reset figure 30. spi master using a separate input for startup status reading master sx872xs slave ss sclk mosi mosi miso/ready miso/ready sclk ss 10k master sx872xs slave ss ss 10k sx_rdy
www.semtech.com page 43 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 9.5 improving noise immunity noise may cause incorrect device operation and incorrect data reception. careful circ uit design and pcb layout prevents much of the problems . noise immunity can be improv ed using the following methods: keep spi lines on the pcb away from noisy lines and devices such as switchers. terminate spi lines at the device using termination resistors as shown in figure 31 . the recommended value for theses resistors is around 100 . the sclk, miso, mosi and ss lines can also be decoupled with capacitors to increase noise performance. the values of r and c then depend on the transmission speed of the spi bus. for a transmissi on speed of around 100 khz, an r of 100 and c of 1nf is suggested. for higher transmission speeds, the values of r and c should be reduced accordingly. but if the operating environment is very noisy, larger values of r and c must be selected, and the transmission speed should be reduced. figure 31. resistors to improve noise immunity between master and slave master sx872xs slave ss sclk mosi mosi miso/ready miso/ready sclk ss 100 100 100 10k
www.semtech.com page 44 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 10 register memory map and description 10.1 register map table 21 below describes the register/memory map that can be accessed through the spi interface. it indicates the register name, register address and the register contents. 10.2 registers descriptions the register descriptions are presented here in ascending order of register address. some registers carry several individual data fields of various sizes; from single-bit valu es (e.g. flags), upwards. some data fields are spread across multiple registers. after power on reset the registers will have the values indicated in the tables "reset" column. please write the reserved bits with their reset values. table 21. register map address register bit description rc register 0x30 regrcen 1 rc oscillator control gpio registers 0x40 regout 8 d0 and d1 pads data output and direction control 0x41 regin 4 d0 and d1 pads input data 0x44 regsoftreset spi software reset adc registers 0x50 regacoutlsb 8 lsb of adc result 0x51 regacoutmsb 8 msb of adc result 0x52 regaccfg0 8 adc conversion control 0x53 regaccfg1 8 adc conversion control 0x54 regaccfg2 8 adc conversion control 0x55 regaccfg3 8 adc conversion control 0x56 regaccfg4 8 adc conversion control 0x57 regaccfg5 8 adc conversion control mode register 0x70 regmode 8 chip operating mode register
www.semtech.com page 45 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 10.2.1 rc register 10.2.2 gpio registers table 22. regrcen[0x30] bit bit name mode reset description 7:1 - r 0000000 reserved 0 rcen rw 1 enables rc oscillator. set 0 for low power mode. table 23. regout[0x40] bit bit name mode reset description 7:6 - r 11 reserved 5 d1dir rw 1 d1 pad direction. 1 : output 0 : input 4 d0dir rw 1 d0 pad direction. 1 : output 0 : input 3:2 - rw 00 reserved 1 d1out rw 0 d1 pad output value. only valid when d1dir =1 and vrefd1in =0. see also table 34, page 48 . 0 d0out rw 0 d0 pad output value. only valid when d0dir =1 and vrefd1out =0. see also table 34, page 48 . table 24. regin[0x41] bit bit name mode reset description 7:2 - r 0000 reserved 1 d1in r- d1 pad value 0 d0in r- d0 pad value
www.semtech.com page 46 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 10.2.3 software reset register 10.2.4 zadc registers table 25. regsoftreset[0x44] bit name mode reset description 7:0 softreset rw 00000000 write the 0xde (b11011110) value into this register to reset the device. table 26. regacoutlsb[0x50] bit name mode reset description 7:0 out[7:0] r 00000000 lsb of the adc result table 27. regacoutmsb[0x51] bit name mode reset description 7:0 out[15:8] r 00000000 msb of the adc result table 28. regaccfg0[0x52] bit name mode reset description 7 start rw 0 starts an adc conversion 6:5 setnelconv rw 01 sets the number of elementary conversion to 2 setnelconv . to compensate for offset the signal is chopped between elementary conversion. 4:2 setosr rw 010 sets the adc over-sampling rate of an elementary conversion to 2 3+setosr . 1 continuous rw 0 sets the continuous adc conversion mode 0 sampleshiften rw 0 adc samples can be read directly on the spi see section 9.3.1, page 39 . table 29. regaccfg1[0x53] bit name mode reset description 7:6 ibampadc rw 11 bias current selection for the adc 5:4 ibamppga rw 11 bias current selection for the pga 3 enable rw 0 pga3 enable 2 rw 0 pga2 enable 1 rw 0 pga1 enable 0rw0adc enable
www.semtech.com page 47 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech table 30. regaccfg2[0x54] bit name mode reset description 7:6 setfs rw 00 adc sampling frequency selection 5:4 pga2gain rw 00 pga2 gain selection 3:0 pga2offset rw 0000 pga2 offset selection table 31. regaccfg3[0x55] bit name mode reset description 7 pga1gain rw 0 pga1 gain selection 6:0 pga3gain rw 0001100 pga3 gain selection table 32. regaccfg4[0x56] bit name mode reset description 7 datareadyen rw 0 combined spi miso and adc data ready signal. 0 : combined data ready mode disabled 1 : combined data ready mode enabled see section 9.3.2, page 39 . 6:0 pga3offset rw 0000000 pga3 offset selection table 33. regaccfg5[0x57] bit name mode reset description 7 busy r 0 adc activity flag 6 def rw 0 selects adc and pga default config uration, starts an adc conversion 5:1 amux rw 00000 input channel configuration selector 0 vmux rw 0 reference channel selector 0 : v batt 1 : v ref
www.semtech.com page 48 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 10.2.5 mode registers (1) the chop control is to allow chopping of the internal bandga p reference. this may be useful to help eliminate bandgap relate d internal offset voltage and 1/f noise. the bandgap chop state may be forced high or low, or may be set to toggle during conversion at ei ther the same rate or half the rate of the elementary conversion. (see conversion sequence in the zoomingadc description). (2) the internal charge pump may be forced on when v batt supply is below 3v or off when v batt supply is above 3v. enabling the charge pump increase the current consumption. if the adc is not being run at full rate or full accuracy then it may operate sufficiently well when v batt is less than 3v and internal charge pump forced off. table 34. regmode[0x70] bit name mode reset description 7 - r1reserved 6 - r0reserved 5:4 chopper rw 00 v ref chopping control. note 1 11 : chop at n elconv /2 rate 10 : chop at n elconv rate 01 : chop state=1 00 : chop state=0 3 multforceon rw 0 force charge pump on. takes priority. note 2 2 multforceoff rw 1 force charge pump off. note 2 1 vrefd0out rw 0 enable v ref output on d0 pin 0 vrefd1in rw 0 enable external v ref on d1 pin
www.semtech.com page 49 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11 typical performances 11.1 input impedance the pgas of the zoomingadc are a switched capacitor based bl ocks (see switched capacitor principle section). this means that it does not use resistors to fix gains, but capa citors and switches. this has important implications on the nature of the input impedance of the block. using switched capacitors is the reason why, while a conversion is done, the input impedance on the selected channel of the pgas is inversely proportional to the sampling frequency fs and to stage gain as given in equation 24 . the input impedance observed is the inpu t impedance of the first pga stage that is enabled or the input impedance of the adc if all three stages are disabled. cg multiplied by gain is the equivalent gain capacitor and cp is the parasitic capacitor of the first enabled stage. the values for each zoomingadc bloc are provided in table 35 : note the graphs and tables provided followi ng this note are statistical summary based on limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range and ther efore outside the warranted range. equation 24 table 35. capacitor values acquisition chain stage gain capacitor cg parasitic capacitor cp units pga1 0.45 1.04 pf pga2 0.54 1.5 pf pga3 0.775 1.8 pf adc 2.67 pf () ] [ 1 + ? cp gain cg z in
www.semtech.com page 50 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech table 35 gives typical impedance values for various gain configurations. pga1 (with a gain of 10) and pga2 (with a gain of 10) have each a minimum input impedance of 300 k at fs = 500 khz. pga3 (with a gain of 10) have a minimum input impedance of 250 k at fs = 500 khz. larger input impedance can be obtained by reducing the gain and/or by reducing the over-sampling frequency fs . therefore, with a gain of 1 and a samp ling frequency of 62.5 khz, zin > 10.2 m for pga1 . the input impedance on channels that are not selected is very high (>10m ). 11.1.1 switched capacitor principle basically, a switched capacitor is a way to emulate a resistor by using a capacitor. the capacitors are much easier to realize on cmos technologies and they show a very good matching precision. a resistor is characterized by the current that flows through it (positive current leaves node v 1 ): one can verify that the me an current leaving node v 1 with a capacitor switched at frequency f is: table 36. typical input impedances z in [m ] pga1gain pga2 gain pga3 gain 11012510124810 fs [khz] 62.5 10.26 2.59 7.95 5.05 2.84 2.24 6.25 4.32 2.86 1.87 1.63 125 5.14 1.30 3.99 2.54 1.44 1.11 3.13 2.16 1.43 0.94 0.82 250 2.57 0.65 1.98 1.26 0.71 0.56 1.56 1.08 0.72 0.47 0.41 500 1.29 0.32 0.99 0.63 0.36 0.28 0.78 0.54 0.36 0.24 0.21 figure 32. the switched capacitor principle equation 25 equation 26 v 1 v 2 r v 1 f fv 2 ] [ 2 1 a r v v i ? = ( ) ] [ 2 1 a c v v i ? ? =
www.semtech.com page 51 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech therefore as a mean value, the switched capacitor 1/( f x c ) is equivalent to a resistor. it is important to consider that this is only a mean value. if the curren t is not integrated (low impedance source ), the impedance is infinite during the whole time but the transition. what does it mean for the zoomingadc? if the fs clock is reduced, the mean impedance is increase d. by dividing the fs clock by a factor 10, the impedance is increased by a factor 10. one can reduce the capacitor that is switched by using an amplifier set to its minimal gain. in particular if pga1 is used with gain 1, its mean impedance is 10x bi gger than when it is used with gain 10. one can increase the effective impedance by increasing the electrical bandwidth of the sensor node so that the switching current is absorbed through the sensor before th e switching period is over. measuring the sensor node will show short voltage spikes at the frequency fs, but these wi ll not influence the measureme nt. whereas if the bandwidth of the node is lower, no spikes will arise, but a small offset can be generated by the integration of the charges generated by the switched capacitors, this corresponds to the mean impedance effect. notes: (1) one can increase the mean input impedance of the zoomingadc by lowering the acquisition clock fs . (2) one can increase the mean input impedance of the zoominga dc by decreasing the gain of the first enabled amplifier. (3) one can increase the effective input impedance of the zoomingadc by having a source with a high electrical bandwidth (sensor electri- cal bandwidth much higher than fs ). figure 33. the switched capacitor principle sensor c zoomingadc (model) v 1 f fv 2 sensor impedence node capacitance current integration
www.semtech.com page 52 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.2 frequency response the incremental adc is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital filter. the main function of the digital filter is to remove th e quantization noise introduced by the modulator. this filter determines the frequency response of the transfer function between the output of the adc and the analog input v in . notice that the frequency axes are normaliz ed to one elementary conversion period osr / fs . the plots of figure 34, page 53 also show that the frequency response change s with the number of elementary conversions n elconv performed. in particular, notches appear for n elconv >= 2 these notches occur at: and are repeated every fs / osr. information on the location of these notches is particularly useful when spec ific frequencies must be filtered out by the acquisition system. this chip has no dedicated 50/60 hz reject ion filtering but some rejection can be achieved by using equation 27 and setting the appropriate values of osr , fs and n elconv . for equation 27 table 37. 50/60 hz line rejection examples rejection [hz] f notch [hz] fs [khz] osr [-] n elconv [-] 60 61 125 1024 2 61 250 1024 4 61 500 1024 8 50 53 62.5 1024 8 46 62.5 1024 4 46 125 1024 8 f notch if s ? osr n elconv ? ------------------------------------ - = i 12 n elconv 1 ? () ,, =
www.semtech.com page 53 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech figure 34. frequency response. normalized magnitude vs. frequency for different n elconv filter profile with nelconv = 1 -80 -60 -40 -20 0 0246810 normalized frequency - f x tconv magnitude [db] filter profile with nelconv = 2 -80 -60 -40 -20 0 0246810 normalized frequency - f x tconv magnitude [db] filter profile with nelconv = 4 -80 -60 -40 -20 0 0246810 normalized frequency - f x tconv magnitude [db] filter profile with nelconv = 8 -80 -60 -40 -20 0 0246810 normalized frequency - f x tconv magnitude [db] filter profile with data rate = 61sps -60 -50 -40 -30 -20 -10 0 50 55 60 65 70 frequency [hz] magnitude [db] filter profile with data rate = 46sps or 53sps -60 -50 -40 -30 -20 -10 0 40 45 50 55 60 frequency [hz] magnitude [db]
www.semtech.com page 54 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.3 linearity 11.3.1 integral non-linearity the different pga stages have been designed to find the best compromise between the noise performance, the integral non-linearity and the power consumption. to obtain this, the first stage has th e best noise performance and the third stage the best linearity performance. for large input signals (small pga gains, i.e. up to about 50), the noise added by the pga is very small with respect to the input signal and the second and third stage of the pga should be used to get the best linearity. for small input signal s (large gains, i.e. above 50), the noise level in the pga is important and the first stage of the pga should be used. the following figures show the integral non linearity for different gain settings over the chip temperature range 11.3.1.1 gain 1 v batt =5v; v ref =v batt ; pgas disabled; osr=1024; nelconv=8; fs=250khz; resolution=16bits. figure 35. inl -40c figure 36. inl 25c figure 37. inl 85c figure 38. inl 125c -10 -8 -6 -4 -2 0 2 4 6 8 10 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 v in [v] inl [lsb] inl gain 1 @ -40c -10 -8 -6 -4 -2 0 2 4 6 8 10 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 v in [v] inl [lsb] inl gain 1 @ 25c -10 -8 -6 -4 -2 0 2 4 6 8 10 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 v in [v] inl [lsb] inl gain 1 @ 85c -10 -8 -6 -4 -2 0 2 4 6 8 10 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 v in [v] inl [lsb] inl gain 1 @ 125c
www.semtech.com page 55 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.3.1.2 gain 10 v batt =5v; v ref =v batt ; adc and pga3 enabled; gd 3 =10; osr=1024; nelconv=8; fs=250khz; resolution=16bits. 11.3.1.3 gain 100 v batt =5v; v ref =v batt ; adc, pga2 and pga3 enabled; gd 2 =10; gd 3 =10; osr=1024; nelconv=8; fs=250khz; resolution=16bits. figure 39. inl -40c figure 40. inl 25c figure 41. inl 85c figure 42. inl 125c -10 -8 -6 -4 -2 0 2 4 6 8 10 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 v in [v] inl [lsb] inl gain 10 @ -40c -10 -8 -6 -4 -2 0 2 4 6 8 10 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 v in [v] inl [lsb] inl gain 10 @ 25c -10 -8 -6 -4 -2 0 2 4 6 8 10 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 v in [v] inl [lsb] inl gain 10 @ 85c -10 -8 -6 -4 -2 0 2 4 6 8 10 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 v in [v] inl [lsb] inl gain 10 @ 125c -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 v in [v] inl [lsb] inl gain 100 @ -40c -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 v in [v] inl [lsb] inl gain 100 @ 25c
www.semtech.com page 56 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.3.1.4 gain 1000 v batt =5v; v ref =v batt; adc, pga3, pga2, pga1 enabled; gd 1 =10, gd 2 =10, gd 3 =10; osr=1024; n elconv =8; fs=250khz; resolution=16bits. figure 43. inl -40c figure 44. inl 25c figure 45. inl 85c figure 46. inl 125c figure 47. inl -40c figure 48. inl 25c figure 49. inl 85c figure 50. inl 125c -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 v in [v] inl [lsb] inl gain 100 @ 85c -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 v in [v] inl [lsb] inl gain 100 @ 125c -200 -150 -100 -50 0 50 100 150 200 -0.002 -0.0015 -0.001 -0.000 5 0 0.0005 0.001 0.0015 0.002 v in [v] inl [lsb] inl gain 1000 @ -40c -200 -150 -100 -50 0 50 100 150 200 -0.002 -0.0015 -0.001 -0.000 5 0 0.0005 0.001 0.0015 0.002 v in [v] inl [lsb] inl gain 1000 @ 25c -200 -150 -100 -50 0 50 100 150 200 -0.002 -0.0015 -0.001 -0.000 5 0 0.0005 0.001 0.0015 0.002 v in [v] inl [lsb] inl gain 1000 @ 85c -200 -150 -100 -50 0 50 100 150 200 -0.002 -0.0015 -0.001 -0.000 5 0 0.0005 0.001 0.0015 0.002 v in [v] inl [lsb] inl gain 1000 @ 125c
www.semtech.com page 57 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.3.2 differential non-linearity the differential non-linearity is generated by the adc . the pga does not add differential non-linearity. figure 51 shows the differential non-linearity. 11.4 noise ideally, a constant input voltage v in should result in a constant output code . however, because of circuit noise, the output code may vary for a fixed input voltage. thus, a statistical analysis on the output code of 1200 conversions for a constant input voltage was performed to derive the equivalent noise levels of pga1 , pga2 , and pga3 . the extracted rms output noise of pga1 , 2 , and 3 are given in table 38, page 59 : standard output deviation and output rms noise voltage. figure 51. differential non-linearity of the adc converter
www.semtech.com page 58 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech v n1 , v n2 , and v n3 are the output rms noise figures of table 38 , gd 1 , gd 2 , and gd 3 are the pga gains of stages 1 to 3 respectively. v refn,wb is the wide band noise on the reference voltage. the simple noise model of figure 52 is used to estimate the equivalent input referred rms noise v n,in of the acquisition chain in the model of figure 54, page 59 . this is given by the relationship: on the numerator of equation 28 : 1 the first parenthesis is the pga1 ga in amplifier contribution to noise 2 the second parenthesis is the pga2 gain amplifier contribution to noise 3 the third parenthesis is the pga3 gain amplifier contribution to noise 4 the fourth parenthesis is pga2 and pga3 offset amplifiers contributions to noise 5 the last parenthesis is the contribution of the noise on the references of the adc figure 52. simple noise model for pgas and adc equation 28 pga1 pga2 pga3 adc vin vin vin vin voff voff vref analog inputs reference inputs v in,adc v ref,adc vss vref ac2 ac3 ac4 ac5 ac6 ac7 vss vbatt vss vref s v refn,wb v n1 v n2 v n3 v in gains: offsets: gd 1 gd 2 gd off2 gd 3 gd off3 ( ) () [] rms v n osr gd v gd gd gd gd v gd v gd gd v gd v v elconv tot wb refn tot off off wb refn tot n n n in n 2 2 , 2 3 2 2 , 2 3 2 2 1 2 2 1 1 2 , 2 1 ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? =
www.semtech.com page 59 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech as shown in equation 28 , noise can be reduced by increasing osr and n elconv (increases the adc averaging effect, but reduces noise). figure 53 shows the distribution for the adc alone ( pga1 , 2 , and 3 bypassed). quantization noise is dominant in this case, and, thus, the adc thermal noise is below 16 bits. as an example, consider the system where: gd 2 = 10 ( gd 1 = 1; pga3 bypassed), osr = 512, n elconv = 2, v ref = 5 v. in this case, the noise contribution v n1 of pga1 is dominant over that of pga2 . using equation 28, page 58 , we get: v n,in = 6.4 v (rms) at the input of the acquisition chain, or, equivalently, 0.85 lsb at the output of the adc . considering 0.2 v (rms) maximum signal amplitude, the signal-to-noise ratio is 90db. table 38. pga noise measurement (n = 16bits, osr = 512, n elconv = 2, v ref = 5v) parameter pga1 pga2 pga3 output rms noise [uv] v n1 = 205 v n2 = 340 v n3 = 365 figure 53. adc noise (pga1, 2 & 3 bypassed, osr = 512, n elconv = 2) figure 54. total input referred noise 0 20 40 60 80 -5 -4 -3 -2 -1 0 1 2 3 4 5 output code deviation from mean value [lsb] occurences [% of total samples] pga1 pga2 pga3 adc vin vin vin vin voff voff vref analog inputs reference inputs v in,adc v ref,adc vss vref ac2 ac3 ac4 ac5 ac6 ac7 vss vbatt vss vref s v n,in v in
www.semtech.com page 60 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.5 gain error and offset error gain error is defined as the amount of deviation between the ideal transfer function (theoretical equation 19, page 30 ) and the measured transfer function (with the offset error removed). the actual gain of the different stages can vary depending on the fabrication tolerances of the different elements. although these tolerances are specified to a maximum of 3%, they will be most of the time around 0.5%. moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. fina lly, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. figure 55 shows gain error drift vs. temperature for different pga gains. the curves are expressed in% of full-scale range ( fsr ) normalized to 25c. offset error is defined as the output code error for a zero volt input (ideally, output code = 0). the offset of the adc and the pga1 stage are completely suppressed if n elconv > 1. the measured offset drift vs. temperature curves for different pga gains are depicted in figure 56 . the output offset error, expressed in lsb for 16-bit setting, is normalized to 25c. notice that if the adc is used alone, the output offset error is below +/-1 lsb and has no drift. figure 55. gain error vs. temperature for different gains f igure 56. offset error vs. temperature for different gains normalized to 25c -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 -50 -25 0 25 50 75 100 temperature [c] gain error [% of fsr] 1 5 20 100 normalized to 25c -40 -20 0 20 40 60 80 100 -50 -25 0 25 50 75 100 temperature [c] output offset error [lsb] 1 5 20 100
www.semtech.com page 61 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 11.6 power consumption as mentioned in section 6.4, page 16 the charge pump must be enabled if v batt is below 3v. figure 57 plots the variation of current consumption with supply voltage v batt , as well as the distribution between the 3 pga stages and the adc (see table 39, page 62 ). in this case the charge pump is forced on for v batt < 4.2v and forced off for v batt > 4.2v. as shown in figure 58 , if lower sampling frequency is used, the curr ent consumption can be lowered by reducing the bias currents of the pgas and the adc with registers ibamppga and ibampadc. (in figure 58 , ibamppga/adc = '11', '10', '00' for fs = 500, 250, 62.5 khz respectively. in this case the charge pump is forced on for v batt < 4.2v and forced off for v batt > 4.2v. figure 57. current consumptio n vs. supply voltage and pgas figure 58. current consumption vs. temperature and adc sampling frequency 200 300 400 500 600 700 800 900 1'000 1'100 22.533.544.555.5 v batt [v] i dd [ua] adc adc+pga1 adc+pga12 adc+pga123 200 300 400 500 600 700 800 900 1'000 1'100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v batt [v] i dd [ua] 62.5khz, ibias = 0.25 125khz, ibias = 0.25 250khz, ibias = 0.5 500khz, ibias = 1
www.semtech.com page 62 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech current consumption vs. temperature is depicted in figure 59 , showing the increase between -40 and +125c. figure 59. current consumption vs. temperature and supply voltage table 39. typical current distribution in ac quisition chain (n = 16 bits, fs = 250khz) supply adc pga1 pga2 pga3 total unit v batt = 2.4v 207 70 51 78 406 ua v batt = 3.5v 282 82 61 91 516 v batt = 5.5v 338 103 67 98 606 600 700 800 900 1000 1100 1200 1300 -40 -20 0 20 40 60 80 100 120 temperature [c] i dd [ua] vbatt = 2.4v vbatt = 3.5v vbatt = 5.5v
www.semtech.com page 63 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech family overview this chapter gives an overview of similar devices based on the zoomingadc but with different features or packages. each part is described in its own datasheet. 12 comparison table table 40. family comparison table part number sx8723c sx8724c sx8725c sx8723s SX8724S sx8725s package mlpd-w-12 4x4 mlpq-16 4x4 mlpd-w-12 4x4 mlpq-16 4x4 mlpq-16 4x4 mlpq-16 4x4 protocol i2c i2c i2c spi spi spi gpio d0 i2c addr, digital io or vref out i2c addr, digital io or vref out i2c add, digital io or vref out digital io or vref out digital io or vref out digital io or vref out d1 i2c addr, digital io or vref in i2c addr, digital io or vref in i2c addr, digital io or vref in digital io or vref out. digital io or vref in digital io or vref in d2 n.a. digital io n.a. n.a. n.a. n.a. d3 n.a. digital io n.a. n.a. n.a. n.a. differential input channels 231231
www.semtech.com page 64 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 13 comparison by package pinout i2c versions spi versions sx8723c (top view) ac4 1 2 3 4 5 6 7 8 9 10 11 12 ac5 vbatt vss ready d1 ac3 ac2 vpump scl sda d0 ac5 vbatt vss n.c. sx8723s (top view) ac2 vpump sclk mosi d0 ready miso/ready ss d1 ac3 n.c. ac4 1 2 3 4 56 78 9 10 11 12 13 14 15 16 ac5 vbatt vss ac7 sx8724c (top view) ac2 vpump scl sda d0 ready d2 d3 d1 ac3 ac6 ac4 1 2 3 4 56 78 9 10 11 12 13 14 15 16 ac5 vbatt vss ac7 SX8724S (top view) ac2 vpump sclk mosi ready ac3 ac6 ac4 1 2 3 4 56 78 9 10 11 12 13 14 15 16 d0 miso/ready ss d1 sx8725c (top view) n.c. 1 2 3 4 5 6 7 8 9 10 11 12 n.c. vbatt vss ready d1 ac3 ac2 vpump scl sda d0 n.c. vbatt vss n.c. sx8725s (top view) ac2 vpump sclk mosi ready ac3 n.c. n.c. 1 2 3 4 56 78 9 10 11 12 13 14 15 16 d0 miso/ready ss d1
www.semtech.com page 65 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech mechanical 14 pcb layout considerations pcb layout considerations to be taken when using the SX8724S are relatively si mple to get the highest performances out of the zoomingadc. the most important to achieve good performances out the zoomingadc is to have a good voltage reference. the SX8724S has alread y an internal reference that is good enough to get the best performances with a minimal amount of external components, but, in case an external reference is needed this one must be as clean as possible in order to get the desired performance. separating the digital from the analog lines will be also a good choice to reduce the noise induced by th e digital lines. it is also advised to have separated ground planes for digital and analog signals with the shortest ret urn path, as well as making the power su pply lines as wider as possible and to have good decoupling capacitors. 15 how to evaluate for evaluation purposes SX8724Sevk evaluation kit can be or dered. this kit connects to any pc using a usb port. a software gives the user the ability to control the SX8724S registers as well as gett ing the raw data from the zoomingadc and displaying it on the "graphical user inte rface". for more information please look at semtech web site ( http://www.semtech.com/ analog-controllers-s ensors-converters/ ).
www.semtech.com page 66 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 16 package outline drawing: mlpq-w16-4x4-ep1 figure 60. package outline drawing 0.08 0.30 16 0.25 2.55 - 0.00 0.70 2.80 0.35 2.70 - 0.05 0.80 (0.20) 0.10 0.65 bsc 0.30 0.40 0.50 2 1 bbb cab seating plane c n e/2 aaa c controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. 1. 2. notes: - - indicator (laser mark) pin 1 dimensions n bbb aaa a2 a1 e1 d1 dim l e e d a b max millimeters min nom 3.90 4.00 4.10 3.90 4.00 4.10 2.55 2.70 2.80 d a b e a1 a2 d1 e1 lxn e/2 bxn e d/2 a
www.semtech.com page 67 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 17 land pattern drawing: mlpq-w16-4x4-ep1 figure 61. land pattern drawing y c z p y x g k h .189 .026 .016 .033 .122 .106 .106 4.80 0.40 0.85 0.65 2.70 2.70 3.10 dim (3.95) millimeters dimensions (.156) inches 1. controlling dimensions are in millimeters (angles in degrees). thermal vias in the land pattern of the exposed pad 3. shall be connected to a system ground plane. functional performance of the device. failure to do so may compromise the thermal and/or 4. square package - dimensions apply in both " x " and " y " directions. k h g z (c) x p this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 2.
www.semtech.com page 68 advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition revision 1.0 february 2011 ? semtech 18 tape and reel specification mlp/qfn (0.70mm - 1.00mm package thickness) single sprocket holes tolerances for ao & bo are +/- 0.20mm tolerances for ko is +/- 0.10mm tolerance for pocket pitch is +/- 0.10mm tolerance for tape width is +/-0.30mm trailer and leader length are minimum required length package orientation and feed direction figure 62. direction of feed figure 63. user direction of feed table 41. tape and reel specifications pkg size carrier tape (mm) reel tape width (w) pocket pitch (p) ao bo ko reel size (in) reel width (mm) trailer length (mm) leader length (mm) qty per reel 4x4 12 8 4.35 4.35 1.10 7/13 12.4 400 400 1000/3000 direction of feed direction of feed mlp (square) mlp (rectangular)
revision 1.0 february 2011 ? semtech www.semtech.com page 69 iso9001 certified semtech corporation advanced co mmunications & sensing products contact information e-mail: sales@semtech.com or acsupport@semtech.com internet: http://www.semtech.com usa 200 flynn road, camarillo, ca 93012-8790. tel: +1 805 498 2111 fax: +1 805 498 3804 far east 12f, no. 89 sec. 5, nanking e. road, taipei, 105, twn, r.o.c. tel: +886 2 2748 3380 fax: +886 2 2748 3390 europe semtech ltd., units 2 & 3, park court, premier way, abbe y park industrial estate, ro msey, hampshire, so51 9dn. tel: +44 (0)1794 527 600 fax: +44 (0)1794 527 601 ? semtech 2010 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not fo rm part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication ther eof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installati on, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. semtech products are not designed, intended, authoriz ed or warranted to be suitable for use in life- support applications, devices or systems or othe r critical applications . inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs damages and atto rney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. advanced communications & sensing datasheet SX8724S zoomingadc for sensin g data acquisition

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